Current methods for manufacturing a three-dimensional thin-film solar cell (3-D TFSC) include forming a 3-Dimensional thin-film silicon substrate (3-D TFSS) using a silicon template.
FIGS. 1A and 1B illustrate a self-supporting three-dimensional honey-comb prism thin-film silicon substrate (3-D TFSS) according to U.S. application Ser. No. 11/868,489. From this 3-D TFSS, innovative silicon solar cells that have low-cost, high efficiency and light weight may be manufactured. FIG. 1A is a top view of a 3-D TFSS prior to its release from a silicon template and FIG. 1B is a cross-sectional view of a 3-D TFSS prior to its release from a silicon template.
Methods for manufacturing a 3-D TFSS such as the 3-D TFSS in FIGS. 1A and 1B, which is made of in-situ-doped epitaxial Si thin film, are disclosed in U.S. application Ser. No. 11/868,489 entitled “METHODS FOR MANUFACTURING THREE-DIMENSIONAL THIN-FILM SOLAR CELLS.” First, trenches are etched into template 14 in a honeycomb pattern by deep reactive ion etching (DRIE) of silicon. Template 14 is often in the range of 500-750 micron meters thick. Next, porous silicon layer 12 is formed on the template top surface, preferably by anodic etching in HF solution. Porous silicon layer 12 is often in the range of 0.5-5 micron meters thick. Then epitaxial (or multi-crystalline) silicon layer 16 is grown on top of porous silicon layer 12 and fills the trenches. Silicon layer 16 is often in the range of 5-50 micron meters thick. After opening border definition trench 10, buried thin porous silicon layer 12 is exposed at trench bottom and serves as a sacrificial layer to be etched away and/or mechanically fractured. As a result, epitaxial silicon layer 16 is released from the template for subsequent device processing. The 3-D TFSS, made of released epitaxial silicon layer 16, will go through other process steps (including doping and metallization) for making solar cells. Silicon template 14 will be then cleaned and re-used to produce multiple released substrates.
The template re-use process includes a new layer of porous silicon formation, epitaxial silicon growth, border definition trench formation and the subsequent release of the 3-D TFSS. The template then may be re-used in multiple cycles for the purpose of reducing the silicon material consumption in making the solar cells that have 3-dimensional micro structures.
FIGS. 2A and 2B illustrate schematic drawings of another 3-D TFSS design. FIG. 2A is a top view of an inverted pyramidal 3-D TFSS prior to its release from a silicon template and FIG. 2B is a cross-sectional view of an inverted pyramidal 3-D TFSS to its release from a silicon template. Instead of using a honey-comb trench structural design as in FIGS. 1A and 1B, here the silicon template uses a staggered array of inverted pyramid cavity structures for the template design. A masking layer defines the pattern of pyramidal structures on the template. The inverted pyramid cavities are then etched by anisotropical wet silicon etching, such as KOH or TMAH, into template 22. As result of this etching, only crystallographic silicon planes are formed on the template surfaces. (111) planes form the sidewalls of the inverted pyramid cavities and (100) planes form the top of the template surface. Further, the pattern may involve staggered large and small cavities to improve the rigidity of the manufactured substrate, shown in FIG. 2B as small pyramidal cavity 28 and large pyramidal cavity 30.
Template 22 is often in the range of 500-750 micron meters thick. Next, porous silicon layer 24 is formed on the template top surface, preferably by anodic etching in HF solution. Porous silicon layer 24 is often in the range of 0.5-5 micron meters thick. Then epitaxial (or multi-crystalline) silicon layer 26 is grown on top of porous silicon layer 12 and fills the trenches. Silicon layer 26 is often in the range of 5-50 micron meters thick. After opening border definition trench 20, buried thin porous silicon layer 24 is exposed at trench bottom and serves as a sacrificial layer to be etched away and/or mechanically fractured. As a result, epitaxial silicon layer 26 is released from the template for subsequent device processing. The released 3-D TFSS, epitaxial silicon layer 26, will go through other process steps (including doping and metallization) for making solar cells. Silicon template 22 will then be cleaned and re-used to produce multiple released substrates.
In addition to the above methods for manufacturing a 3-D TFSS, “SUBSTRATE RELEASE METHODS AND APPARATUS”, U.S. application Ser. No. 12/473,811 discloses methods for releasing a 3-D TFSS substrate from a re-usable silicon template. As disclosed in the incorporated application, the physical and/or chemical separation of the 3-D TFSS is initiated and propagated within the porous silicon layer that resides between the 3-D TFSS and the template.
According to the above reference application, the porous silicon layer is produced from the template silicon surface layer for every template re-use cycle using an anodic etch process. In order to use the template multiple times, the total thickness of the porous silicon layer is in the range of 0.1 μm to 10 μm, preferably in the lower range of less than 2 μm. There are two purposes of the porous silicon layer. The first purpose is to serve as a sacrificial layer to facilitate the releasing of the silicon substrate from the template. To ease the release of the silicon substrate, it is desirable that the porous silicon layer have a high porosity. The second purpose of the porous silicon layer is to serve as a seed mono-crystalline silicon layer to facilitate the epitaxial silicon growth (the silicon substrate itself). To initiate high quality epitaxial silicon growth it is desirable that the porous silicon layer have a low porosity. A bi-layer or double-layer porous silicon structure is often used so that the two porosities may be optimized relatively independently. More specifically, the first porous silicon layer furthest from the template is made in a low porosity range, preferably in the range of 10% to 30%, while the second porous silicon layer closest to the template is made subsequently in a high porosity range, preferably in the range of 60% to 85%. It is to be noted that the there may be an edge exclusion surface area on the wafer that does not get converted into porous silicon. Normally, this area may extend from the wafer edge to about 5 mm inwards. This porous silicon edge exclusion is caused by the space used for O-ring sealing during porous silicon formation process.
Also according to the above referenced application, the 3-D TFSS layer is made of epitaxial grown mono-crystalline silicon, typically in the thickness range of 5 μm to 50 μm range. Alternatively, the 3-D TFSS may be made of a deposited multi-crystalline or amorphous silicon layer, in which case the buried sacrificial layer is not limited to porous silicon. Thin film materials, such as an oxide layer of 0.1 μm to 1 μm may also be used as the sacrificial layer between the 3-D TFSS to be released and the re-usable silicon template. It is also to be noted the epitaxial silicon growth usually covers the entire silicon template top surfaces including the wafers edges. And unless some special wafers edge covering/masking method is applied, the entire porous silicon surface is buried in the epitaxial silicon layer.
As shown in FIGS. 1A and 1B and FIGS. 2A and 2B, in order to release the 3-D TFSS from the re-usable template, an enclosed border definition trench (shown as border definition trench 10 in FIGS. 1A and 1B and border definition trench 20 in FIGS. 2A and 2B) has to be made into the 3-D TFSS layer and must serve the following purposes:                (1) Define the boundary of the 3-D TFSS, so that the shape and size of the solar cell may be defined;        (2) Separate the 3-D TFSS to be released from the its material deposited on the wafer periphery;        (3) Expose the buried sacrificial porous layer at trench bottom, so that the releasing of the 3-D TFSS could be initiated or ended at the trench boundary for the mechanical release methods. In the chemical-etching-assisted releasing cases, the exposed trench bottom provides an etching front for chemical etchant to reach the buried sacrificial layer.        
Additionally, following are specific technical requirements for trench formation:                (1) The process of making the trench should not affect the surface and bulk material properties of the 3-D TFSS layer;        (2) The trench depth should be stopped and kept within the thin sacrificial layer. Trench depth shallower than the 3-D TFSS thickness will prevent chemical etchant from reaching the porous sacrificial layer, while a deeper trench depth will cut into the silicon template and make the trench forming process difficult to control in the next template re-use cycle;        (3) The trench lateral profile may be square or a quasi-square with rounded corners to maximize a square area that is taken from a round wafer surface;        (4) It is desirable to avoid having the trench extended or started from the wafers edge in order to prevent wafer cracking that most likely is initiated from wafer edge defects. As an example, saw blade cutting is to be avoided since it has to be started from the wafer edge and a drop-in saw may not be practical.        
Given the above needs and requirements of making the border definition trenches, laser cutting, deep reactive ion etching (DRIE), wet chemical (such as KOH) silicon etching and mechanical scribing have been tested. However none of these methods are able to control the trench depth within the thin sacrificial layer.
FIG. 3 is a SEM photo of a shallow trench made by laser cutting using a Nd:YAG solid state laser with wave length of 532 nm. Using this laser cutter, the main technical challenge was the inefficient removal of silicon debris during laser cutting which caused local overheating variations. As a result, the trench surfaces are rough and depth of the trench is difficult to control. As an example, it is difficult to have a depth tolerance of less than +/−3 um for a 50 um deep trench cut. And in this case, the trench depth variation is larger the total thickness of the sacrificial porous silicon layer of the present disclosure. Therefore, to cut the trench by laser to a depth within the thin porous silicon layer is not practical.
FIG. 4 is a cross-sectional photo showing a shallow 50 um wide trench made by DRIE etching using a photo lithographically defined photo-resist mask 40. The trench is made in 50 um thick epitaxial Si layer 46 to expose 3 um thick porous Si layer 48.
The DRIE silicon etching is based on the well-known Bosch process, which uses alternating steps of etching with SF6 gas and surface passivation with C4F8 gas in plasma. The etching and passivation cycles result in a straight trench sidewall with a small amount of waving surface, commonly called scalloping. When the DRIE process is used in forming trenches to release the 3-D TFSS of the disclosed subject matter, there are three phenomenons to be noted. First, because there is no etching stop layer under the epitaxial silicon layer, an over etching is required and the trench bottom ends in bulk silicon template 44. Second, when the DRIE etching process reaches the buried porous silicon layer, local charging usually occurs and results in lateral etching to form notches, shown as lateral notches 42. Third, the local charging will also cause surface roughness and form grass-like silicon microstructures at trench bottom, as visible in FIG. 4.
The challenge of using laser cutting/scribing for making border definition trenches that do not cut through the wafer is the control of trench depth. To make a narrow trench and stop the trench bottom within the buried thin porous silicon layer, no more no less, is not practical given the state of art laser machining technologies.
The issues of depth control, lateral notching and grass forming may not affect the formation of a border definition trench and the subsequent 3-D TFSS release in a first template use cycle. However, these issues may affect process controls in subsequent template re-use cycle.
The TFSS film (epitaxial silicon) thickness variation is another factor that makes trench depth control difficult. In a typical epitaxial silicon growth on a 200 mm silicon wafer, the epitaxial silicon layer thickness uniformity is 5% within wafer, 6% within run and 2% from run to run. As an example, for a 50 um thick layer, a 5% uniformity translates into +/−2.5 um thickness variation, which is equivalent to if not more than the disclosed porous silicon layer thickness.
In addition to the above factors, the wafer non-flatness, or bowing, may also cause difficulties for trench depth control. As an example, when laser cutting is used, the non-flatness will cause difficulty of the laser beam focusing control, which results in poor trench depth and surface control.